The present invention relates to a data processor having a memory controller capable of controlling an external memory synchronously with a clock, specifically to a technique effective in use for a microcontroller provided with an interface controller for a DDR-SDRAM (double data rate SDRAM) memory.
The synchronous memory that behaves synchronously with a clock, represented by an SDRAM (Synchronous Dynamic Random Access Memory), is widely used for a frame buffer for graphics and a main memory in a CPU (Central Processing Unit) and so forth. For example, the SDRAM has plural memory banks, and each memory bank has an address decoder, memory array, sense amplifier array, and so forth, and each is made independently controllable. The plural memory banks are configured to behave in pipeline, which makes a high-speed access possible. Especially, the synchronous memory with a DDR configuration performs data input/output with the outside synchronously with both the rise edge and fall edge of a clock, which further increases the access speed compared to the synchronous memory with an SDR (single data rate) configuration. The patent document 1 discloses a multi-bank SDRAM. The patent document 2 discloses a system controller incorporating graphic ports and an SDRAM controller. The synchronous memory is connected to such a system controller that performs the access control thereto.
[Paten Document 1]
Japanese Unexamined Patent Publication No. Hei 10(1998)-189889
[Paten Document 2]
Japanese Unexamined Patent Publication No. 2000-132503 (FIG. 6)